Sciweavers

105 search results - page 18 / 21
» Scalable shared memory LTL model checking
Sort
View
CAV
2008
Springer
108views Hardware» more  CAV 2008»
15 years 1 months ago
Reducing Concurrent Analysis Under a Context Bound to Sequential Analysis
This paper addresses the analysis of concurrent programs with shared memory. Such an analysis is undecidable in the presence of multiple procedures. One approach used in recent wor...
Akash Lal, Thomas W. Reps
ICPP
2008
IEEE
15 years 6 months ago
Scioto: A Framework for Global-View Task Parallelism
We introduce Scioto, Shared Collections of Task Objects, a lightweight framework for providing task management on distributed memory machines under one-sided and globalview parall...
James Dinan, Sriram Krishnamoorthy, D. Brian Larki...
108
Voted
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
15 years 6 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
HIPC
2005
Springer
15 years 5 months ago
Mobile Pipelines: Parallelizing Left-Looking Algorithms Using Navigational Programming
Abstract. Parallelizing a sequential algorithm—i.e., manually or automatically converting it into an equivalent parallel distributed algorithm—is an important problem. Ideally,...
Lei Pan, Ming Kin Lai, Michael B. Dillencourt, Lub...
115
Voted
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
14 years 10 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...