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ICS
2009
Tsinghua U.
15 years 2 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
LCTRTS
2001
Springer
15 years 2 months ago
Evaluating and Optimizing Thread Pool Strategies for Real-Time CORBA
Strict control over the scheduling and execution of processor resources is essential for many fixed-priority real-time applications. To facilitate this common requirement, the Re...
Irfan Pyarali, Marina Spivak, Ron Cytron, Douglas ...
HCW
1998
IEEE
15 years 1 months ago
Implementing Distributed Synthetic Forces Simulations in Metacomputing Environments
A distributed, parallel implementation of the widely used Modular Semi-Automated Forces ModSAF Distributed Interactive Simulation DIS is presented, with Scalable Parallel Processo...
Sharon Brunett, Dan Davis, Thomas Gottschalk, Paul...
HPCA
1998
IEEE
15 years 1 months ago
The Effectiveness of SRAM Network Caches in Clustered DSMs
The frequency of accesses to remote data is a key factor affecting the performance of all Distributed Shared Memory (DSM) systems. Remote data caching is one of the most effective...
Adrian Moga, Michel Dubois
ASPLOS
1998
ACM
15 years 1 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...