One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...
Many practical applications generate irregular, nonbalanced divide-and-conquer trees which have different depths, possibly also different numbers of successors at different levels...
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
Alok N. Choudhary, Wei-keng Liao, Donald Weiner, P...
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...