433 search results - page 17 / 87 » Scale in Chip Interconnect requires Network Technology |
ISCAS
2008
IEEE
15 years 4 months ago
2008
IEEE
— By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way t...
3DIC
2009
IEEE
15 years 4 months ago
2009
IEEE
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
77
Voted
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
DSRT
2003
IEEE
15 years 2 months ago
2003
IEEE
Continued research into distributed agent-based systems and evolving web based technologies are opening up tremendous possibilities for the deployment of large scale and highly ex...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...