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» Scale in Chip Interconnect requires Network Technology
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DAC
2006
ACM
15 years 10 months ago
Are carbon nanotubes the future of VLSI interconnections?
Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLS...
Kaustav Banerjee, Navin Srivastava
ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
15 years 3 months ago
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting....
Zhonghai Lu, Bei Yin, Axel Jantsch
CODES
2003
IEEE
15 years 2 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
15 years 4 months ago
SCARAB: a single cycle adaptive routing and bufferless network
As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has...
Mitchell Hayenga, Natalie D. Enright Jerger, Mikko...
ASYNC
2005
IEEE
142views Hardware» more  ASYNC 2005»
15 years 3 months ago
An Asynchronous Router for Multiple Service Levels Networks on Chip
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementa...
Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Ey...