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» Scale in Chip Interconnect requires Network Technology
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74
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IPPS
2006
IEEE
15 years 3 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
HPCA
2009
IEEE
15 years 10 months ago
A low-radix and low-diameter 3D interconnection network design
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao ...
71
Voted
ICC
2007
IEEE
145views Communications» more  ICC 2007»
15 years 4 months ago
Click on a Cluster: A Viable Approach to Scale Software-Based Routers
—Extensible software-based routers running on commodity off-the-shelf hardware and open-source operating systems have been motivated by the progress in hardware technologies and ...
Qinghua Ye, Mike H. MacGregor
DAC
2011
ACM
13 years 9 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
TVLSI
2002
144views more  TVLSI 2002»
14 years 9 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail