433 search results - page 22 / 87 » Scale in Chip Interconnect requires Network Technology |
NETWORKING
2007
14 years 11 months ago
2007
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A funda...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
DFT
2007
IEEE
15 years 4 months ago
2007
IEEE
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
DSN
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
NOCS
2007
IEEE
15 years 3 months ago
2007
IEEE
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...