433 search results - page 25 / 87 » Scale in Chip Interconnect requires Network Technology |
ISCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
73
Voted
DAC
2010
ACM
14 years 11 months ago
2010
ACM
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
ISCA
2007
IEEE
15 years 4 months ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
ISLPED
2009
ACM
15 years 4 months ago
2009
ACM
This paper presents an evaluation to determine the importance of the accurate thermal characterization for several elements of a semiconductor device. Specifically, it evaluates ...
70
Voted
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptima...