433 search results - page 26 / 87 » Scale in Chip Interconnect requires Network Technology |
SIGCOMM
2012
ACM
13 years 3 days ago
2012
ACM
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— Networks-on-chip (NoCs) are a scalable interconnect solution to large scale multiprocessor systems on chip and are rapidly becoming reality. As the ratio of embedded co...
ISCA
2007
IEEE
15 years 4 months ago
2007
IEEE
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
ICETET
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...