433 search results - page 29 / 87 » Scale in Chip Interconnect requires Network Technology |
PDP
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
This paper presents figures of merit and error formulae to determine which interconnects require volume discretization in the GHZ range. Most of the previous work focused mainly o...
106
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CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
15 years 1 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
DAC
2001
ACM
15 years 10 months ago
2001
ACM
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
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AINA
2007
IEEE
15 years 4 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...