433 search results - page 31 / 87 » Scale in Chip Interconnect requires Network Technology |
NOCS
2009
IEEE
15 years 4 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
81
Voted
ICC
2008
IEEE
15 years 4 months ago
2008
IEEE
—The recent years have seen an enormous advance in wireless communication technology and a wide spread of various types of wireless networks. It requires effective inter-networki...
ICPP
2000
IEEE
15 years 2 months ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
ASPLOS
1998
ACM
15 years 1 months ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...