433 search results - page 34 / 87 » Scale in Chip Interconnect requires Network Technology |
68
Voted
DAC
1999
ACM
15 years 2 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
Advancing technology drives design technology and thus design automation EDA . How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
CF
2007
ACM
15 years 1 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
DATE
2010
IEEE
15 years 1 months ago
2010
IEEE
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...