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» Scale in Chip Interconnect requires Network Technology
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DATE
2002
IEEE
96views Hardware» more  DATE 2002»
15 years 2 months ago
A Linear-Centric Simulation Framework for Parametric Fluctuations
The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...
Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
DSN
2011
IEEE
13 years 9 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
WOSP
2000
ACM
15 years 2 months ago
Expressing meaningful processing requirements among heterogeneous nodes in an active network
Active Network technology envisions deployment of virtual execution environments within network elements, such as switches and routers. As a result, nonhomogeneous processing can ...
Virginie Galtier, Kevin L. Mills, Yannick Carlinet...
SECON
2010
IEEE
14 years 7 months ago
Coexistence-Aware Scheduling for Wireless System-on-a-Chip Devices
Abstract--Today's mobile devices support many wireless technologies to achieve ubiquitous connectivity. Economic and energy constraints, however, drive the industry to impleme...
Lei Yang, Vinod Kone, Xue Yang, York Liu, Ben Y. Z...
SAINT
2005
IEEE
15 years 3 months ago
On Scalable Modeling of TCP Congestion Control Mechanism for Large-Scale IP Networks
In this paper, we propose an analytic approach of modeling a closed-loop network with multiple feedback loops using fluid-flow approximation. Specifically, we model building bl...
Hiroyuki Ohsaki, Juñya Ujiie, Makoto Imase