433 search results - page 37 / 87 » Scale in Chip Interconnect requires Network Technology |
96
Voted
GI
2009
Springer
15 years 2 months ago
2009
Springer
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets)...
80
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
ITNG
2007
IEEE
15 years 3 months ago
2007
IEEE
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
CAISE
2003
Springer
15 years 2 months ago
2003
Springer
Abstract. Peer-oriented computing is an attempt to weave interconnected machines into the fabric of the Internet. Service-oriented computing (exemplified by web-services), on the ...
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...