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» Scale in Chip Interconnect requires Network Technology
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ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
15 years 6 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
ECCTD
2011
72views more  ECCTD 2011»
13 years 9 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic
EUROCRYPT
2007
Springer
15 years 3 months ago
Non-wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-Bit
Significant progress in the design of special purpose hardware for supporting the Number Field Sieve (NFS) has been made. From a practical cryptanalytic point of view, however, no...
Willi Geiselmann, Rainer Steinwandt
74
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DSD
2009
IEEE
118views Hardware» more  DSD 2009»
15 years 4 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
JNSM
2000
122views more  JNSM 2000»
14 years 9 months ago
Communications Systems Driven by Software Agent Technology
The application of software agent technology to the management of communications' infrastructures is a challenging domain as it requires management on different time scales a...
Alex L. Hayzelden, John Bigham, Stefan Poslad, Phi...