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» Scale in Chip Interconnect requires Network Technology
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DATE
2008
IEEE
75views Hardware» more  DATE 2008»
15 years 4 months ago
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization
With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperat...
Srinivasan Murali, Almir Mutapcic, David Atienza, ...
TPDS
1998
129views more  TPDS 1998»
14 years 9 months ago
The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics
—Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconn...
W. Stephen Lacy, José Cruz-Rivera, D. Scott...
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
15 years 2 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
14 years 7 months ago
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs
Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-...
Young-Joon Lee, Rohan Goel, Sung Kyu Lim
HPCA
2007
IEEE
15 years 10 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...