Sciweavers

433 search results - page 44 / 87
» Scale in Chip Interconnect requires Network Technology
Sort
View
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
15 years 3 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
DATE
2009
IEEE
161views Hardware» more  DATE 2009»
15 years 4 months ago
Co-design of signal, power, and thermal distribution networks for 3D ICs
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...
Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad ...
GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
15 years 3 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ISCA
2000
IEEE
118views Hardware» more  ISCA 2000»
15 years 1 months ago
Smart Memories: a modular reconfigurable architecture
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and lo...
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, Willi...