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» Scale in Chip Interconnect requires Network Technology
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JCC
2007
121views more  JCC 2007»
14 years 9 months ago
Speeding up parallel GROMACS on high-latency networks
: We investigate the parallel scaling of the GROMACS molecular dynamics code on Ethernet Beowulf clusters and what prerequisites are necessary for decent scaling even on such clust...
Carsten Kutzner, David van der Spoel, Martin Fechn...
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
15 years 6 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
15 years 3 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
JETC
2008
127views more  JETC 2008»
14 years 8 months ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar
MSS
2003
IEEE
93views Hardware» more  MSS 2003»
15 years 3 months ago
IP SAN - From iSCSI to IP-Addressable Ethernet Disks
The initial iSCSI products provide a means to connect FC SAN islands across IP networks. This paper describes the implementation of an IP-SAN where the disk subsystem is a virtual...
Peter Wang, Robert E. Gilligan, Henry Green, Jeff ...