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» Scale in Chip Interconnect requires Network Technology
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ICCAD
2001
IEEE
100views Hardware» more  ICCAD 2001»
15 years 6 months ago
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
Kaustav Banerjee, Amit Mehrotra
INFOCOM
2008
IEEE
15 years 4 months ago
Distributed Operator Placement and Data Caching in Large-Scale Sensor Networks
Abstract—Recent advances in computer technology and wireless communications have enabled the emergence of stream-based sensor networks. In such sensor networks, real-time data ar...
Lei Ying, Zhen Liu, Donald F. Towsley, Cathy H. Xi...
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
15 years 4 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
NOCS
2009
IEEE
15 years 4 months ago
Silicon-photonic clos networks for global on-chip communication
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Sco...