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» Scale in Chip Interconnect requires Network Technology
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MSS
2007
IEEE
153views Hardware» more  MSS 2007»
15 years 4 months ago
Hybrid Host/Network Topologies for Massive Storage Clusters
The high demand for large scale storage capacity calls for the availability of massive storage solutions with high performance interconnects. Although cluster file systems are rap...
Asha Andrade, Ungzu Mun, Dong Hwan Chung, Alexande...
FPL
1997
Springer
75views Hardware» more  FPL 1997»
15 years 1 months ago
Thermal monitoring on FPGAs using ring-oscillators
In this paper, a temperature-to-frequency transducer suitable for thermal monitoring on FPGAs is presented. The dependence between delay and temperature is used to produce a freque...
Eduardo I. Boemo, Sergio López-Buedo
IEEEHPCS
2010
14 years 8 months ago
Analytical modeling and evaluation of network-on-chip architectures
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Ta...
ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
15 years 3 months ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
INFOCOM
2007
IEEE
15 years 4 months ago
End-to-End Flow Fairness Over IEEE 802.11-Based Wireless Mesh Networks
—Economies of scale make IEEE 802.11 an attractive technology for building wireless mesh networks (WMNs). However, the IEEE 802.11 protocol exhibits serious link-layer unfairness...
Ashish Raniwala, Pradipta De, Srikant Sharma, Rupa...