433 search results - page 55 / 87 » Scale in Chip Interconnect requires Network Technology |
ICC
2008
IEEE
15 years 4 months ago
2008
IEEE
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
SAC
2009
ACM
15 years 4 months ago
2009
ACM
The prediction of the correct secondary structures of large RNAs is one of the unsolved challenges of computational molecular biology. Among the major obstacles is the fact that a...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
CSC
2006
2006
An Adaptive Method for Flow Simulation in Three-Dimensional Heterogeneous Discrete Fracture Networks
14 years 11 months ago
Natural fractured media are highly unpredictable because of existing complex structures at the fracture and at the network levels. Fractures are by themselves heterogeneous objects...
ITNG
2006
IEEE
15 years 3 months ago
2006
IEEE
—In this paper, we address the scheduling problem for Clos-network switches with no buffers at the central stage. Existing scheduling (dispatching) algorithms for this type of sw...