433 search results - page 60 / 87 » Scale in Chip Interconnect requires Network Technology |
SBCCI
2006
ACM
15 years 3 months ago
2006
ACM
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
SBRN
2000
IEEE
15 years 2 months ago
2000
IEEE
d Articles >> Table of Contents >> Abstract VI Brazilian Symposium on Neural Networks (SBRN'00) p. 24 Adaptation of Parameters of BP Algorithm Using Automata Hamid...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
65
Voted
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
78
Voted
APCSAC
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...