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» Scale in Chip Interconnect requires Network Technology
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HOTI
2008
IEEE
15 years 4 months ago
HPP Switch: A Novel High Performance Switch for HPC
The high performance switch plays a critical role in the high performance computer (HPC) system. The applications of HPC not only demand on the low latency and high bandwidth of t...
Dawei Wang, Zheng Cao, Xinchun Liu, Ninghui Sun
NETWORK
2008
153views more  NETWORK 2008»
14 years 9 months ago
IEEE 802.11s: WLAN mesh standardization and high performance extensions
In recent years, remarkable market competition and economy of scale has resulted in the price erosion of wireless devices for consumer electronics. Especially for wireless data ne...
Guido R. Hiertz, Yunpeng Zang, Sebastian Max, Thom...
RTAS
1997
IEEE
15 years 1 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
83
Voted
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
15 years 3 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
14 years 11 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong