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» Scale in Chip Interconnect requires Network Technology
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FCCM
1999
IEEE
122views VLSI» more  FCCM 1999»
15 years 1 months ago
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
Andrew A. Chien, Jay H. Byun
OTM
2007
Springer
15 years 3 months ago
A Bluetooth-Based JXME Infrastructure
Abstract. Over the last years, research efforts have led the way to embed computation into the environment. Much attention is drawn to technologies supporting dynamicity and mobil...
Carlo Blundo, Emiliano De Cristofaro
UPP
2004
Springer
15 years 3 months ago
Autonomic Computing: An Overview
Abstract. The increasing scale complexity, heterogeneity and dynamism of networks, systems and applications have made our computational and information infrastructure brittle, unma...
Manish Parashar, Salim Hariri
ASPDAC
2009
ACM
159views Hardware» more  ASPDAC 2009»
15 years 2 months ago
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapa...
DFMA
2005
IEEE
143views Multimedia» more  DFMA 2005»
15 years 3 months ago
Efficient Media Asset Transfer in a Unified Framework Managing Broadcasting Systems
File transfer acts an increasing role in digital TV studios and especially for their interconnections. Using adequate file formats to exchange data presents several advantages: lo...
Mathrin Body, Bernard Cousin