433 search results - page 65 / 87 » Scale in Chip Interconnect requires Network Technology |
100
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ATAL
2003
Springer
15 years 2 months ago
2003
Springer
We apply the multi-agent system (MAS) platform to the task of biological network simulation. In this paper, we describe the simulation of signal transduction (ST) networks using t...
SLIP
2005
ACM
15 years 3 months ago
2005
ACM
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
ISCA
1994
IEEE
15 years 1 months ago
1994
IEEE
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
LCN
2006
IEEE
15 years 3 months ago
2006
IEEE
— The paper presents a thought experiment as to the feasibility of using large scale wireless sensor networks as a vehicle for high level scientific investigation. The discussion...
102
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IPPS
2003
IEEE
15 years 2 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...