Sciweavers

433 search results - page 66 / 87
» Scale in Chip Interconnect requires Network Technology
Sort
View
88
Voted
HOTI
2002
IEEE
15 years 2 months ago
Architecture and Hardware for Scheduling Gigabit Packet Streams
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
CLUSTER
2006
IEEE
15 years 3 months ago
Cluster-based IP Router: Implementation and Evaluation
IP routers are now increasingly expected to do more than just traditional packet forwarding – they must be extensible as well as scalable. It is a challenge to design a router a...
Qinghua Ye, Mike H. MacGregor
CORR
2010
Springer
116views Education» more  CORR 2010»
14 years 4 months ago
Simulating Cyber-Attacks for Fun and Profit
We introduce a new simulation platform called Insight, created to design and simulate cyber-attacks against large arbitrary target scenarios. Insight has surprisingly low hardware...
Ariel Futoransky, Fernando Miranda, José Ig...
PERCOM
2010
ACM
14 years 8 months ago
Robopedia: Leveraging Sensorpedia for web-enabled robot control
Abstract— There is a growing interest in building Internetscale sensor networks that integrate sensors from around the world into a single unified system. In contrast, robotics ...
Richard Edwards, Lynne E. Parker, David Resseguie
102
Voted
3DIC
2009
IEEE
263views Hardware» more  3DIC 2009»
15 years 29 days ago
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwa...