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» Scale in Chip Interconnect requires Network Technology
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74
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DAC
2004
ACM
15 years 10 months ago
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computati...
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik...
HPCC
2007
Springer
15 years 3 months ago
Performance Prediction Based Resource Selection in Grid Environments
Deploying Grid technologies by distributing an application over several machines has been widely used for scientific simulations, which have large requirements for computational r...
Peggy Lindner, Edgar Gabriel, Michael M. Resch
BTW
2007
Springer
136views Database» more  BTW 2007»
15 years 3 months ago
System P: Completeness-driven Query Answering in Peer Data Management Systems
Abstract: Peer data management systems (PDMS) are a highly dynamic, decentralized infrastructure for large-scale data integration. They consist of a dynamic set of autonomous peers...
Armin Roth, Felix Naumann
75
Voted
MICRO
2007
IEEE
159views Hardware» more  MICRO 2007»
15 years 3 months ago
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
Kypros Constantinides, Onur Mutlu, Todd M. Austin,...
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 3 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar