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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
15 years 6 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
SIGCOMM
2009
ACM
15 years 6 months ago
Towards automated performance diagnosis in a large IPTV network
IPTV is increasingly being deployed and offered as a commercial service to residential broadband customers. Compared with traditional ISP networks, an IPTV distribution network (i...
Ajay Anil Mahimkar, Zihui Ge, Aman Shaikh, Jia Wan...
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
15 years 5 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
ICCV
2007
IEEE
15 years 5 months ago
Dense Multiscale Motion Extraction from Cardiac Cine MR Tagging using HARP Technology
We propose an operational method to extract the left ventricle (LV) systole dynamics using HARmonic Phase (HARP) images extracted from tagged cardiac MR sequences. Established tec...
Luc Florack, Hans C. van Assen, Avan Suinesiaputra
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
15 years 5 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...