234 search results - page 11 / 47 » Scaling, Power and the Future of CMOS |
68
Voted
ICCD
2005
IEEE
15 years 6 months ago
2005
IEEE
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
ISCAS
2008
IEEE
15 years 4 months ago
2008
IEEE
— A fully differential translinear 3-phase sinusoidal oscillator architecture is presented. The architecture is meant for BiCMOS implementation and uses only NPN devices, typical...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
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GLVLSI
2009
IEEE
15 years 1 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...