234 search results - page 14 / 47 » Scaling, Power and the Future of CMOS |
CDES
2006
14 years 11 months ago
2006
Abstract--This paper describes an architecture of FPGAlike fabric for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack an...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
100
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MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
As DRAM and other charge memories reach scaling limits, resistive memories, such as phase change memory (PCM), may permit continued scaling of main memories. However, while PCM ma...
NOCS
2010
IEEE
14 years 7 months ago
2010
IEEE
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
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GI
2009
Springer
15 years 2 months ago
2009
Springer
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets)...