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» Scaling, Power and the Future of CMOS
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EH
2002
IEEE
105views Hardware» more  EH 2002»
15 years 2 months ago
Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic
The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5GHz have been reported. However, to make the idea practical, serious power management an...
Channakeshav, Kuan Zhou, Russell P. Kraft, John F....
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
15 years 3 months ago
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperat...
José Luis Rosselló, Vicens Canals, S...
CICC
2011
106views more  CICC 2011»
13 years 9 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
DATE
2005
IEEE
112views Hardware» more  DATE 2005»
15 years 3 months ago
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
ISCAS
2005
IEEE
117views Hardware» more  ISCAS 2005»
15 years 3 months ago
Electrical and optical on-chip interconnects in scaled microprocessors
Abstract— Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper ...
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas...