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» Scaling, Power and the Future of CMOS
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ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Decomposition based approach for synthesis of multi-level threshold logic circuits
Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the ...
Tejaswi Gowda, Sarma B. K. Vrudhula
85
Voted
ISLPED
2003
ACM
149views Hardware» more  ISLPED 2003»
15 years 2 months ago
Elements of low power design for integrated systems
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
Sung-Mo Kang
ISLPED
1997
ACM
106views Hardware» more  ISLPED 1997»
15 years 1 months ago
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Kha...
74
Voted
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
15 years 10 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
ISLPED
2000
ACM
99views Hardware» more  ISLPED 2000»
15 years 2 months ago
Practical considerations of clock-powered logic
Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that ...
William C. Athas