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» Scaling, Power and the Future of CMOS
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VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
15 years 10 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
GLVLSI
2007
IEEE
114views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Design of mixed gates for leakage reduction
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
Frank Sill, Jiaxi You, Dirk Timmermann
TVLSI
2010
14 years 4 months ago
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
Mohammad Taherzadeh-Sani, Anas A. Hamoui
CORR
2008
Springer
76views Education» more  CORR 2008»
14 years 9 months ago
Fabrication of MEMS Resonators in Thin SOI
A simple and fast process for micro-electromechanical (MEM) resonators with deep sub-micron transduction gaps in thin SOI is presented in this paper. Thin SOI wafers are important...
Daniel Grogg, Nicoleta Diana Badila-Ciressan, Adri...
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
15 years 6 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...