234 search results - page 19 / 47 » Scaling, Power and the Future of CMOS |
ECCTD
2011
13 years 9 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are b...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
SAMOS
2007
Springer
15 years 3 months ago
2007
Springer
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however...
ISLPED
2009
ACM
15 years 2 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...