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» Scaling, Power and the Future of CMOS
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ISCAS
2007
IEEE
92views Hardware» more  ISCAS 2007»
15 years 4 months ago
A Study on Impact of Leakage Current on Dynamic Power
— Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now beco...
Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
15 years 6 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
CASES
2006
ACM
15 years 3 months ago
Methods for power optimization in distributed embedded systems with real-time requirements
Dynamic voltage scaling and sleep state control have been shown to be extremely effective in reducing energy consumption in CMOS circuits. Though plenty of research papers have st...
Razvan Racu, Arne Hamann, Rolf Ernst, Bren Mochock...
ISVLSI
2002
IEEE
93views VLSI» more  ISVLSI 2002»
15 years 2 months ago
Temperature Variable Supply Voltage for Power Reduction
The scaling trend of MOSFETs requires the supply and the threshold voltages to be reduced in future generations. Although the supply voltage is reduced, the total power dissipatio...
Kaveh Shakeri, James D. Meindl
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
15 years 4 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...