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» Scaling, Power and the Future of CMOS
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IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
15 years 3 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
82
Voted
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
15 years 10 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
15 years 3 months ago
Designing MRF based error correcting circuits for memory elements
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
15 years 6 months ago
Thermal-Aware Clustered Microarchitectures
As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it ...
Pedro Chaparro, José González, Anton...
ISCAS
2006
IEEE
214views Hardware» more  ISCAS 2006»
15 years 3 months ago
Multimode digital SMPS controller IC for low-power management
This paper introduces a novel low-power digital future, are expected to run at frequencies beyond 10 MHz. In controller for high frequency dc-dc switch-mode power supplies addition...
N. Rahman, A. Parayandeh, Kun Wang, A. Prodic