234 search results - page 25 / 47 » Scaling, Power and the Future of CMOS |
ERSA
2003
14 years 11 months ago
2003
The availability of SiGe HBT devices has opened a door for Gigahertz FPGAs. However, the large device power consumption limits its scale. In order to solve this problem, a Multipl...
97
Voted
GLVLSI
2010
IEEE
15 years 2 months ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
DSN
2008
IEEE
15 years 4 months ago
2008
IEEE
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
DSN
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...