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» Scaling, Power and the Future of CMOS
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GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
123
Voted
PLDI
2003
ACM
15 years 2 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
75
Voted
DATE
2007
IEEE
91views Hardware» more  DATE 2007»
15 years 4 months ago
Transient fault prediction based on anomalies in processor events
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
Satish Narayanasamy, Ayse Kivilcim Coskun, Brad Ca...
APCSAC
2007
IEEE
15 years 1 months ago
Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters
Many years of CMOS technology scaling have resulted in increased power densities and higher core temperatures. Power and temperature concerns are now considered to be a primary cha...
Daniel C. Vanderster, Amirali Baniasadi, Nikitas J...
IJHPCA
2008
75views more  IJHPCA 2008»
14 years 9 months ago
Towards Ultra-High Resolution Models of Climate and Weather
We present a speculative extrapolation of the performance aspects of an atmospheric general circulation model to ultra-high resolution and describe alternative technological paths...
Michael F. Wehner, Leonid Oliker, John Shalf