234 search results - page 27 / 47 » Scaling, Power and the Future of CMOS |
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practi...
INFOCOM
2008
IEEE
15 years 4 months ago
2008
IEEE
Abstract—Exponential bandwidth scaling has been a fundamental driver of the growth and popularity of the Internet. However, increases in bandwidth have been accompanied by increa...
79
Voted
SPE
2010
14 years 8 months ago
2010
This paper surveys the research on power management techniques for high performance systems. These include both commercial high performance clusters and scientific high performanc...