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» Scaling, Power and the Future of CMOS
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ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 1 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
93
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DAC
1998
ACM
15 years 10 months ago
Reducing Power in High-Performance Microprocessors
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is ...
Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav M...
ISCA
2009
IEEE
178views Hardware» more  ISCA 2009»
15 years 4 months ago
Thread motion: fine-grained power management for multi-core systems
Dynamic voltage and frequency scaling (DVFS) is a commonly-used powermanagement scheme that dynamically adjusts power and performance to the time-varying needs of running programs...
Krishna K. Rangan, Gu-Yeon Wei, David Brooks
HPCA
2003
IEEE
15 years 10 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...