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» Scaling, Power and the Future of CMOS
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MICRO
2009
IEEE
113views Hardware» more  MICRO 2009»
15 years 4 months ago
The BubbleWrap many-core: popping cores for sequential acceleration
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
79
Voted
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
15 years 3 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
74
Voted
DAC
2004
ACM
15 years 10 months ago
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant e
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit M...
84
Voted
DAC
2004
ACM
15 years 1 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
62
Voted
ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Reliability-aware design for nanometer-scale devices
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
David Atienza, Giovanni De Micheli, Luca Benini, J...