Sciweavers

234 search results - page 32 / 47
» Scaling, Power and the Future of CMOS
Sort
View
DAC
2005
ACM
15 years 10 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
59
Voted
IPPS
2009
IEEE
15 years 4 months ago
Efficient microarchitecture policies for accurately adapting to power constraints
In the past years Dynamic Voltage and Frequency Scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process...
Juan M. Cebrian, Juan L. Aragón, José...
EMSOFT
2010
Springer
14 years 7 months ago
Power-aware temporal isolation with variable-bandwidth servers
Variable-bandwidth servers (VBS) control process execution speed by allocating variable CPU bandwidth to processes. VBS enables temporal isolation of EDF-scheduled processes in th...
Silviu S. Craciunas, Christoph M. Kirsch, Ana Soko...
80
Voted
IPPS
2005
IEEE
15 years 3 months ago
Power and Energy Profiling of Scientific Applications on Distributed Systems
Power consumption is a troublesome design constraint for emergent systems such as IBM’s BlueGene /L. If current trends continue, future petaflop systems will require 100 megawat...
Xizhou Feng, Rong Ge, Kirk W. Cameron
79
Voted
CASES
2006
ACM
15 years 3 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh