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» Scaling, Power and the Future of CMOS
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ISLPED
2007
ACM
57views Hardware» more  ISLPED 2007»
14 years 11 months ago
Resource area dilation to reduce power density in throughput servers
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
Michael D. Powell, T. N. Vijaykumar
DATE
2009
IEEE
92views Hardware» more  DATE 2009»
15 years 4 months ago
Using randomization to cope with circuit uncertainty
—Future computing systems will feature many cores that run fast, but might show more faults compared to existing CMOS technologies. New software methodologies must be adopted to ...
Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Arde...
81
Voted
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
15 years 4 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
MICRO
2010
IEEE
145views Hardware» more  MICRO 2010»
14 years 7 months ago
Combating Aging with the Colt Duty Cycle Equalizer
Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. Th...
Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mi...
VLSISP
2010
148views more  VLSISP 2010»
14 years 8 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...