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» Scaling, Power and the Future of CMOS
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93
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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 2 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
MICRO
2008
IEEE
119views Hardware» more  MICRO 2008»
15 years 4 months ago
The StageNet fabric for constructing resilient multicore systems
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
FIS
2008
14 years 11 months ago
A First Step Towards Stream Reasoning
While reasoners are year after year scaling up in the classical, time invariant domain of ontological knowledge, reasoning upon rapidly changing information has been neglected or f...
Emanuele Della Valle, Stefano Ceri, Davide Frances...
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
15 years 2 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
109
Voted
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
15 years 3 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...