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» Scaling, Power and the Future of CMOS
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MSS
2005
IEEE
175views Hardware» more  MSS 2005»
15 years 3 months ago
High Performance Storage System Scalability: Architecture, Implementation and Experience
The High Performance Storage System (HPSS) provides scalable hierarchical storage management (HSM), archive, and file system services. Its design, implementation and current domin...
Richard W. Watson
79
Voted
SEMWEB
2004
Springer
15 years 3 months ago
Small Can Be Beautiful in the Semantic Web
In 1984, Peter Patel-Schneider published a paper [1] entitled Small can be Beautiful in Knowledge Representation in which he advocated for limiting the expressive power of knowledg...
Marie-Christine Rousset
59
Voted
ASPDAC
2006
ACM
93views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Electrothermal analysis and optimization techniques for nanoscale integrated circuits
Abstract— With technology scaling, on-chip power densities are growing steadily, leading to the point where temperature has become an important consideration in the design of ele...
Yong Zhan, Brent Goplen, Sachin S. Sapatnekar
TC
2011
14 years 4 months ago
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
IISWC
2009
IEEE
15 years 4 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee