234 search results - page 37 / 47 » Scaling, Power and the Future of CMOS |
PACS
2004
Springer
15 years 3 months ago
2004
Springer
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
82
Voted
DAC
2008
ACM
15 years 10 months ago
2008
ACM
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...