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» Scaling, Power and the Future of CMOS
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APCSAC
2005
IEEE
15 years 3 months ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope
ICCD
2008
IEEE
126views Hardware» more  ICCD 2008»
15 years 4 months ago
Accelerating search and recognition with a TCAM functional unit
Abstract— World data is increasing rapidly, doubling almost every three years[1][2]. To comprehend and use this data effectively, search and recognition (SR) applications will de...
Atif Hashmi, Mikko Lipasti
AAAI
2012
13 years 5 hour ago
Dynamic Matching via Weighted Myopia with Application to Kidney Exchange
In many dynamic matching applications—especially high-stakes ones—the competitive ratios of prior-free online algorithms are unacceptably poor. The algorithm should take distr...
John P. Dickerson, Ariel D. Procaccia, Tuomas Sand...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 1 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 2 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri