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» Scaling, Power and the Future of CMOS
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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
15 years 3 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
FCCM
2007
IEEE
122views VLSI» more  FCCM 2007»
15 years 1 months ago
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
TLDI
2010
ACM
247views Formal Methods» more  TLDI 2010»
15 years 6 months ago
F-ing modules
ML modules are a powerful language mechanism for decomposing programs into reusable components. Unfortunately, they also have a reputation for being “complex” and requiring fa...
Andreas Rossberg, Claudio V. Russo, Derek Dreyer
DATE
2009
IEEE
229views Hardware» more  DATE 2009»
15 years 4 months ago
Health-care electronics The market, the challenges, the progress
— Exploding health care demands and costs of aging and stressed populations necessitate the use of more in-home monitoring and personalized health care. Electronics hold great pr...
Wolfgang Eberle, Ashwin S. Mecheri, Thi Kim Thoa N...
76
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MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
15 years 3 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...