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» Scaling, Power and the Future of CMOS
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ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun ...
DATE
2005
IEEE
158views Hardware» more  DATE 2005»
15 years 3 months ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
15 years 3 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
15 years 3 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
15 years 6 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda