234 search results - page 5 / 47 » Scaling, Power and the Future of CMOS |
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
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TIM
2010
14 years 4 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
ASPDAC
2009
ACM
15 years 2 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
ISVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...